1. Field of the Invention
The present invention relates to packaging of integrated circuit chips and more particularly concerns an improved three-dimensional package of stacked integrated circuit chips.
2. Description of Related Art
As electronic circuits become larger and more complex, increased efforts continue to be directed toward the goal of decreasing size of circuit packages. In some types of multi-chip modules, many integrated circuit chips are mounted side by side in close proximity to one another on a multi-layered substrate so that adjacent chips may be connected to one another by means of connecting leads that extend in a number of different planes, thereby decreasing horizontal dimensions of the package at the expense of some increase in vertical dimension.
Integrated circuit chips have also been stacked vertically one upon another to provide decreased size, weight and power as compared to conventional single chip or multiple horizontally aligned chip packaging. However, because of the large number of chip connecting pads, which may be in excess of four hundred on a single chip, for example, it is difficult, in prior arrangements, for chip stacking to adequately provide interconnections from all of the chip pads to one another as desired, or to external circuitry. In prior chip stacking arrangements interconnecting leads between chips on different levels are provided at the sides of the stack. Leads are routed from each chip connecting pad to the side of the stack, and interconnections are made in the form of vertical connectors or vertical buses that extend along the exterior sides of the stack. Because the vertical surface area of the sides of the stack is limited, the number of input/output connections between the chip connecting pads of the chips of a stack and connecting elements at the outside of the stack is itself severely limited. In prior chip stacks, connecting leads from the chip connecting pads have been routed to one side of the stack so as to most conveniently form the vertical interconnects between stack layers and connections. This has been done in the past by adding metallization or additional leads on the chip or using other interconnect techniques, such as tape automated bonding. These techniques require special processing of the chips or wafers and add considerable cost to the stacking process. Without the use of special chip or wafer processing to allow stacking in the prior art, the input/output connections for interconnecting stack layers are limited in number. Thus, standard chips that are not specially processed for stacking cannot be stacked without severe limitations on input/output connections.
Accordingly, it is an object of the present invention to provide integrated circuit chip packaging that avoids or minimizes above mentioned problems.